mirror of
https://github.com/minexew/Shrine.git
synced 2026-05-26 18:10:58 +00:00
tramplersheikhs
411 lines
11 KiB
HolyC
411 lines
11 KiB
HolyC
// vim: set ft=c:
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#include "::/Adam/HwSupp/Pci"
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// Significantly based on http://wiki.osdev.org/AMD_PCNET
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#define PCNET_DEVICE_ID 0x2000
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#define PCNET_VENDOR_ID 0x1022
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#define PCNET_COMMAND_IOEN (1<<0)
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#define PCNET_COMMAND_MEMEN (1<<1)
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#define PCNET_COMMAND_BMEN (1<<2)
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#define PCNET_COMMAND_SCYCEN (1<<3)
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#define PCNET_COMMAND_MWIEN (1<<4)
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#define PCNET_COMMAND_VGASNOOP (1<<5)
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#define PCNET_COMMAND_PERREN (1<<6)
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#define PCNET_COMMAND_ADSTEP (1<<7)
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#define PCNET_COMMAND_SERREN (1<<8)
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#define PCNET_COMMAND_FBTBEN (1<<9)
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#define PCNET_STATUS_FBTBC (1<<7)
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#define PCNET_STATUS_DATAPERR (1<<8)
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#define PCNET_STATUS_DEVSEL_BIT 9
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#define PCNET_STATUS_STABORT (1<<11)
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#define PCNET_STATUS_RTABORT (1<<12)
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#define PCNET_STATUS_RMABORT (1<<13)
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#define PCNET_STATUS_SERR (1<<14)
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#define PCNET_STATUS_PERR (1<<15)
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#define PCNET_WD_RESET 0x14
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#define PCNET_DW_RDP 0x10
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#define PCNET_DW_RAP 0x14
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#define PCNET_DW_RESET 0x18
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#define PCNET_CSR0_INIT (1<<0)
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#define PCNET_CSR0_STRT (1<<1)
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#define PCNET_CSR0_STOP (1<<2)
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#define PCNET_CSR0_IENA (1<<6)
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#define PCNET_CSR0_IDON (1<<8)
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#define PCNET_CSR0_TINT (1<<9)
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#define PCNET_CSR0_RINT (1<<10)
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#define PCNET_CSR3_BSWP (1<<2)
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#define PCNET_CSR3_IDONM (1<<8)
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#define PCNET_CSR3_TINTM (1<<9)
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#define PCNET_CSR3_RINTM (1<<10)
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#define PCNET_CSR4_TXSTRT (1<<3)
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#define PCNET_CSR4_ASTRP_RCV (1<<10)
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#define PCNET_CSR4_APAD_XMT (1<<11)
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#define PCNET_TXFIFO_FULL (-1)
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// TODO: this should be configurable
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#define PCNET_NUM_RX_LOG2 5
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#define PCNET_NUM_TX_LOG2 3
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#define rx_buffer_count (1<<PCNET_NUM_RX_LOG2)
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#define tx_buffer_count (1<<PCNET_NUM_TX_LOG2)
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// Including SrcAddr, DstAddr, EtherType
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// Where does this even belong? NetFifo defines for now.
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//#define ETHERNET_FRAME_SIZE 1548
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#define PCNET_DE_SIZE 16
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class CPCNetBufferSetup {
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U16 mode;
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U8 rlen;
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U8 tlen;
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U8 mac[6];
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U16 reserved;
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U8 ladr[8];
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U32 rxbuf;
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U32 txbuf;
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};
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// Card I/O base
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I64 pcnet_iob = 0;
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U8 my_mac[6];
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// Current Rx/Tx buffer
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I64 rx_buffer_ptr = 0;
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I64 tx_buffer_ptr = 0;
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// Rx/Tx descriptor ring buffers, PCNET_DE_SIZE each
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// _phys are uncached
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U8* rdes_phys;
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U8* tdes_phys;
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U8* rdes;
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U8* tdes;
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U32 rx_buffers; // physical address of actual receive buffers (< 4 GiB)
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U32 tx_buffers; // physical address of actual transmit buffers (< 4 GiB)
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static U0 writeRAP32(U32 val) {
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OutU32(pcnet_iob + PCNET_DW_RAP, val);
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}
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static U32 readCSR32(U32 csr_no) {
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writeRAP32(csr_no);
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return InU32(pcnet_iob + PCNET_DW_RDP);
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}
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static U0 writeCSR32(U32 csr_no, U32 val) {
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writeRAP32(csr_no);
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OutU32(pcnet_iob + PCNET_DW_RDP, val);
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}
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static U0 PCNetReset() {
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InU32(pcnet_iob + PCNET_DW_RESET);
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InU16(pcnet_iob + PCNET_WD_RESET);
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}
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// does the driver own the particular buffer?
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static I64 driverOwns(U8 *des, I64 idx)
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{
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return (des[PCNET_DE_SIZE * idx + 7] & 0x80) == 0;
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}
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static U0 PCNetReadEeprom(I64 offset, U8* buffer, I64 count) {
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while (count) {
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*buffer = InU32(pcnet_iob + offset);
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offset++;
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buffer++;
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count--;
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}
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}
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static I64 PCNetRxPacket(U8** buffer_out, U16* length_out) {
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I64 index = rx_buffer_ptr;
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// packet length is given by bytes 8 and 9 of the descriptor
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// (no need to negate it unlike BCNT above)
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U16* p16 = &rdes[index * PCNET_DE_SIZE + 8];
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U16 length = *p16;
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// increment rx_buffer_ptr;
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rx_buffer_ptr = (rx_buffer_ptr + 1) & (rx_buffer_count - 1);
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*buffer_out = rx_buffers + index * ETHERNET_FRAME_SIZE;
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*length_out = length;
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return index;
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}
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static I64 PCNetReleaseRxPacket(I64 index) {
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rdes[index * PCNET_DE_SIZE + 7] = 0x80;
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return 0;
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}
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static I64 PCNetAllocTxPacket(U8** buffer_out, I64 length, I64 flags) {
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// FIXME: validate length
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flags = flags;
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if (!driverOwns(tdes, tx_buffer_ptr)) {
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return PCNET_TXFIFO_FULL;
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}
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I64 index = tx_buffer_ptr;
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// set the STP bit in the descriptor entry (signals this is the first
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// frame in a split packet - we only support single frames)
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tdes[index * PCNET_DE_SIZE + 7] |= 0x2;
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// similarly, set the ENP bit to state this is also the end of a packet
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tdes[index * PCNET_DE_SIZE + 7] |= 0x1;
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// set the BCNT member to be 0xf000 OR'd with the first 12 bits of the
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// two's complement of the length of the packet
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U16 bcnt = (-length);
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bcnt &= 0xfff;
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bcnt |= 0xf000;
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U16* p16 = &tdes[index * PCNET_DE_SIZE + 4];
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*p16 = bcnt;
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tx_buffer_ptr = (tx_buffer_ptr + 1) & (tx_buffer_count - 1);
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*buffer_out = tx_buffers + index * ETHERNET_FRAME_SIZE;
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return index;
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}
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static I64 PCNetFinishTxPacket(I64 index) {
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// finally, flip the ownership bit back to the card
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tdes[index * PCNET_DE_SIZE + 7] |= 0x80;
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return 0;
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}
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static U0 PCNetInitDE(U32 buf_addr, U8 *des, I64 idx, I64 is_tx) {
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MemSet(&des[idx * PCNET_DE_SIZE], PCNET_DE_SIZE, 0);
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// first 4 bytes are the physical address of the actual buffer
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U32* p32 = &des[idx * PCNET_DE_SIZE];
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*p32 = buf_addr + idx * ETHERNET_FRAME_SIZE;
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// next 2 bytes are 0xf000 OR'd with the first 12 bits of the 2s complement of the length
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U16 bcnt = (-ETHERNET_FRAME_SIZE);
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bcnt &= 0x0fff;
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bcnt |= 0xf000;
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U16* p16 = &des[idx * PCNET_DE_SIZE + 4];
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*p16 = bcnt;
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// finally, set ownership bit - transmit buffers are owned by us, receive buffers by the card
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if (!is_tx)
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des[idx * PCNET_DE_SIZE + 7] = 0x80;
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}
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static I64 PCNetAllocBuffers() {
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I64 i;
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I64 rdes_size = PCNET_DE_SIZE * rx_buffer_count;
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I64 tdes_size = PCNET_DE_SIZE * tx_buffer_count;
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rdes_phys = MAlloc(rdes_size, Fs->code_heap);
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tdes_phys = MAlloc(tdes_size, Fs->code_heap);
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if (rdes_phys + rdes_size > 0x100000000 || tdes_phys + tdes_size > 0x100000000) {
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"$FG,4$PCNetAllocBuffers: rdes_phys=%08Xh tdes_phys=%08Xh\n$FG$", rdes_phys, tdes_phys;
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return -1;
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}
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rdes = rdes_phys + dev.uncached_alias;
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tdes = tdes_phys + dev.uncached_alias;
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I64 rx_buffers_size = ETHERNET_FRAME_SIZE * rx_buffer_count;
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I64 tx_buffers_size = ETHERNET_FRAME_SIZE * tx_buffer_count;
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// TODO: shouldn't these be uncached as well?
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rx_buffers = MAlloc(rx_buffers_size, Fs->code_heap);
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tx_buffers = MAlloc(tx_buffers_size, Fs->code_heap);
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if (rx_buffers + rx_buffers_size > 0x100000000 || tx_buffers + tx_buffers_size > 0x100000000) {
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"$FG,4$PCNetAllocBuffers: rx_buffers=%08Xh tx_buffers=%08Xh\n$FG$", rx_buffers, tx_buffers;
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return -1;
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}
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for (i = 0; i < rx_buffer_count; i++)
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PCNetInitDE(rx_buffers, rdes, i, FALSE);
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for (i = 0; i < tx_buffer_count; i++)
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PCNetInitDE(tx_buffers, tdes, i, TRUE);
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//"rdes: %08Xh\ttdes: %08X\n", rdes, tdes;
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//"rbuf: %08Xh\ttbuf: %08X\n", rx_buffers, tx_buffers;
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return 0;
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}
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interrupt U0 PCNetIrq() {
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U32 csr0 = readCSR32(0);
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while (driverOwns(rdes, rx_buffer_ptr)) {
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//if (csr0 & PCNET_CSR0_RINT) {
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//"Int reason %08X\n", csr0;
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U8* buffer;
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U16 length;
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I64 index = PCNetRxPacket(&buffer, &length);
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if (index >= 0) {
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//"[%d] Rx %d B\n", index, length;
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NetFifoPushCopy(buffer, length);
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PCNetReleaseRxPacket(index);
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}
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writeCSR32(0, csr0 | PCNET_CSR0_RINT);
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}
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*(dev.uncached_alias + LAPIC_EOI)(U32*) = 0;
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}
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static U0 PCNetInit(I64 bus, I64 dev_, I64 fun) {
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CPciDevInfo info;
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PciGetDevInfo(&info, bus, dev_, fun);
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//PciDumpInfo(&info);
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if (info.vendor_id != PCNET_VENDOR_ID || info.device_id != PCNET_DEVICE_ID)
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throw;
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U16 config = PCNET_COMMAND_IOEN | PCNET_COMMAND_BMEN;
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PCIWriteU16(bus, dev_, fun, PCI_REG_COMMAND, config);
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config = PCIReadU16(bus, dev_, fun, PCI_REG_COMMAND);
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pcnet_iob = (PCIReadU32(bus, dev_, fun, PCI_REG_BAR0) & ~(0x0000001f));
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//U32 membase = (PCIReadU32(bus, dev_, fun, PCI_REG_BAR1) & ~(0x0000001f));
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//"PCNet iobase: %016Xh\n", pcnet_iob;
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//"PCNet membase: %08Xh\n", membase;
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// Reset the card to get into defined state
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PCNetReset();
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Sleep(1);
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// Enter 32-bit mode
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OutU32(pcnet_iob + PCNET_DW_RDP, 0);
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// SWSTYLE
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U32 csr58 = readCSR32(58);
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csr58 &= 0xfff0;
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csr58 |= 2;
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writeCSR32(58, csr58);
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PCNetReadEeprom(0, my_mac, 6);
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if (PCNetAllocBuffers() < 0)
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return;
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U8* setup = MAlloc(sizeof(CPCNetBufferSetup), Fs->code_heap);
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CPCNetBufferSetup* u_setup = setup + dev.uncached_alias;
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u_setup->mode = 0; // see CSR15 in spec
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u_setup->rlen = (PCNET_NUM_RX_LOG2 << 4);
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u_setup->tlen = (PCNET_NUM_TX_LOG2 << 4);
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MemCpy(u_setup->mac, my_mac, 6);
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"PCNet MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
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u_setup->mac[0], u_setup->mac[1], u_setup->mac[2], u_setup->mac[3], u_setup->mac[4], u_setup->mac[5];
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u_setup->reserved = 0;
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MemSet(u_setup->ladr, 0, 8);
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u_setup->rxbuf = rdes_phys;
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u_setup->txbuf = tdes_phys;
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U32 p_setup = setup;
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writeCSR32(1, p_setup & 0xffff);
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writeCSR32(2, p_setup >> 16);
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U32 csr3 = readCSR32(3);
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csr3 &= ~PCNET_CSR3_BSWP; // disable big-endian
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csr3 &= ~PCNET_CSR3_RINTM; // enable Rx interruot
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csr3 |= PCNET_CSR3_IDONM; // mask-out Init Done Interrupt
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csr3 |= PCNET_CSR3_TINTM; // mask-out Tx interrupt
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writeCSR32(3, csr3);
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U32 csr4 = readCSR32(4);
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csr4 |= PCNET_CSR4_APAD_XMT; // auto pad transmit
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writeCSR32(4, csr4);
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// Upload configuration
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writeCSR32(0, readCSR32(0) | PCNET_CSR0_INIT | PCNET_CSR0_IENA);
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while (!(readCSR32(0) & PCNET_CSR0_IDON)) {
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Yield;
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}
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// Exit config mode
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U32 csr0 = readCSR32(0);
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csr0 &= ~(PCNET_CSR0_INIT | PCNET_CSR0_STOP);
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csr0 |= PCNET_CSR0_STRT;
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writeCSR32(0, csr0);
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// Init interrupt
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//IntEntrySet(info.interrupt_line, &PCNetIrq, IDTET_IRQ);
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IntEntrySet(0x40, &PCNetIrq, IDTET_IRQ);
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IntEntrySet(0x41, &PCNetIrq, IDTET_IRQ);
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IntEntrySet(0x42, &PCNetIrq, IDTET_IRQ);
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IntEntrySet(0x43, &PCNetIrq, IDTET_IRQ);
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PciRerouteInterrupts(0x40);
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Sleep(100);
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Free(setup);
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}
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I64 EthernetFrameAlloc(U8** buffer_out, U8* src_addr, U8* dst_addr, U16 ethertype, I64 length, I64 flags) {
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U8* frame;
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// APAD_XMT doesn't seem to work in VirtualBox, so we have to pad the frame ourselves
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if (length < 46)
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length = 46;
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I64 index = PCNetAllocTxPacket(&frame, 14 + length, flags);
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if (index < 0)
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return index;
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MemCpy(frame + 0, dst_addr, 6);
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MemCpy(frame + 6, src_addr, 6);
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frame[12] = (ethertype >> 8);
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frame[13] = (ethertype & 0xff);
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*buffer_out = frame + 14;
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return index;
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}
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I64 EthernetFrameFinish(I64 index) {
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return PCNetFinishTxPacket(index);
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}
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U8* EthernetGetAddress() {
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return my_mac;
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}
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I64 EthernetInit() {
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I64 b, d, f;
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if (pcnet_iob != 0)
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return 0;
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if (PciFindByID(PCNET_VENDOR_ID, PCNET_DEVICE_ID, &b, &d, &f)) {
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//"PCNet @ %d:%d:%d\n", b, d, f;
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PCNetInit(b, d, f);
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return 0;
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}
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return -1;
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}
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