Files
2021-07-05 01:10:48 -04:00

154 lines
4.0 KiB
HolyC

Bool TG_Debug = FALSE;
#define TG_COLORS 256
#define TG_WIDTH 320
#define TG_HEIGHT 200
#define VGA_MODE_320x200x256 0
#define VGA_MODE_640x480x16 1
#define VGA_MISC_WRITE 0x3C2
#define VGA_NUM_SEQ_REGS 5
#define VGA_SEQ_INDEX 0x3C4
#define VGA_SEQ_DATA 0x3C5
#define VGA_CRTC_INDEX 0x3D4
#define VGA_CRTC_DATA 0x3D5
#define VGA_NUM_CRTC_REGS 25
#define VGA_NUM_GC_REGS 9
#define VGA_GC_INDEX 0x3CE
#define VGA_GC_DATA 0x3CF
#define VGA_NUM_AC_REGS 21
#define VGA_INSTAT_READ 0x3DA
#define VGA_AC_INDEX 0x3C0
#define VGA_AC_WRITE 0x3C0
Bool TG_VGA_UPDATE = FALSE;
CBGR48 TOS_PALETTE[COLORS_NUM];
CDC *TG_Canvas = DCNew(TG_WIDTH, TG_HEIGHT);
I64 TOS_KEYDEV_FP[26];
U8 TG_VGAMode320x200x256[61] = {
0x63, 0x03, 0x01, 0x0F, 0x00, 0x0E, 0x5F, 0x4F, 0x50, 0x82, 0x54,
0x80, 0xBF, 0x1F, 0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x9C, 0x0E, 0x8F, 0x28, 0x40, 0x96, 0xB9, 0xA3, 0xFF, 0x00, 0x00,
0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, 0xFF, 0x00, 0x01, 0x02, 0x03,
0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E,
0x0F, 0x41, 0x00, 0x0F, 0x00, 0x00};
U8 TG_VGAMode640x480x16[61] = {
0xE3, 0x03, 0x01, 0x08, 0x00, 0x06, 0x5F, 0x4F, 0x50, 0x82, 0x54,
0x80, 0x0B, 0x3E, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xEA, 0x0C, 0xDF, 0x28, 0x00, 0xE7, 0x04, 0xE3, 0xFF, 0x00, 0x00,
0x00, 0x00, 0x03, 0x00, 0x05, 0x0F, 0xFF, 0x00, 0x01, 0x02, 0x03,
0x04, 0x05, 0x14, 0x07, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E,
0x3F, 0x01, 0x00, 0x0F, 0x00, 0x00};
U0 TG_VGASwitchMode(I64 mode) {
I64 i;
U8 *regs;
switch (mode) {
case VGA_MODE_320x200x256:
regs = &TG_VGAMode320x200x256;
break;
case VGA_MODE_640x480x16:
regs = &TG_VGAMode640x480x16;
break;
default:
return;
break;
}
OutU8(VGA_MISC_WRITE, *regs);
regs++;
for (i = 0; i < VGA_NUM_SEQ_REGS; i++) {
OutU8(VGA_SEQ_INDEX, i);
OutU8(VGA_SEQ_DATA, *regs);
regs++;
}
OutU8(VGA_CRTC_INDEX, 0x03);
OutU8(VGA_CRTC_DATA, InU8(VGA_CRTC_DATA) | 0x80);
OutU8(VGA_CRTC_INDEX, 0x11);
OutU8(VGA_CRTC_DATA, InU8(VGA_CRTC_DATA) & ~0x80);
regs[0x03] |= 0x80;
regs[0x11] &= ~0x80;
for (i = 0; i < VGA_NUM_CRTC_REGS; i++) {
OutU8(VGA_CRTC_INDEX, i);
OutU8(VGA_CRTC_DATA, *regs);
regs++;
}
for (i = 0; i < VGA_NUM_GC_REGS; i++) {
OutU8(VGA_GC_INDEX, i);
OutU8(VGA_GC_DATA, *regs);
regs++;
}
for (i = 0; i < VGA_NUM_AC_REGS; i++) {
InU8(VGA_INSTAT_READ);
OutU8(VGA_AC_INDEX, i);
OutU8(VGA_AC_WRITE, *regs);
regs++;
}
InU8(VGA_INSTAT_READ);
OutU8(VGA_AC_INDEX, 0x20);
}
U0 TG_ColorSet(I64 index, I64 r, I64 g,
I64 b) { // Set color value for color 0-255, RGB 0-255.
OutU8(VGAP_REG_WRITE, index);
OutU8(VGAP_PALETTE_DATA, r >> 2);
OutU8(VGAP_PALETTE_DATA, g >> 2);
OutU8(VGAP_PALETTE_DATA, b >> 2);
}
U0 TG_ColorGet(I64 index, I64 *r, I64 *g,
I64 *b) { // Get color value for color 0-255, RGB 0-255.
OutU8(VGAP_REG_READ, index);
r[0] = InU8(VGAP_PALETTE_DATA) << 2;
g[0] = InU8(VGAP_PALETTE_DATA) << 2;
b[0] = InU8(VGAP_PALETTE_DATA) << 2;
}
U0 TG_Flip() {
while ((InU8(VGA_INSTAT_READ) & 1))
;
while (!(InU8(VGA_INSTAT_READ) & 1))
;
MemCpy(VGAM_GRAPHICS, TG_Canvas->body, TG_WIDTH * TG_HEIGHT);
}
Bool TG_KeyDown(I64 sc) { return Bt(kbd.down_bitmap, sc); }
I64 TG_MouseX() { return ms.pos.x / 2; }
I64 TG_MouseY() { return ms.pos.y / 2.4; }
U0 TG_Start() {
I64 i;
GrPaletteGet(&TOS_PALETTE);
LBts(&sys_winmgr_task->task_flags, TASKf_SUSPENDED);
TG_VGASwitchMode(VGA_MODE_320x200x256);
for (i = 0; i < 26; i++) {
TOS_KEYDEV_FP[i] = keydev.fp_ctrl_alt_cbs[i];
keydev.fp_ctrl_alt_cbs[i] = NULL;
}
}
U0 TG_Exit() {
I64 i;
TG_VGASwitchMode(VGA_MODE_640x480x16);
GrPaletteSet(&TOS_PALETTE);
GrPaletteIndicesSet;
VGAFlush;
FifoU8Flush(kbd.scan_code_fifo);
FlushMsgs;
for (i = 0; i < 26; i++) {
keydev.fp_ctrl_alt_cbs[i] = TOS_KEYDEV_FP[i];
}
LBtc(&sys_winmgr_task->task_flags, TASKf_SUSPENDED);
}
U0 TG_Resume() {
// Resume from debugger.
TG_Start;
TG_Debug = FALSE;
G2;
}