mirror of
https://github.com/roytam1/UXP.git
synced 2026-05-26 14:54:25 +00:00
Brian Smith
228 lines
7.4 KiB
C++
228 lines
7.4 KiB
C++
/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*-
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#include "jit/BaselineCompiler.h"
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#include "jit/BaselineIC.h"
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#include "jit/BaselineJIT.h"
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#include "jit/Linker.h"
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#include "jit/SharedICHelpers.h"
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#include "jit/MacroAssembler-inl.h"
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using namespace js;
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using namespace js::jit;
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namespace js {
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namespace jit {
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// ICBinaryArith_Int32
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extern "C" {
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extern MOZ_EXPORT int64_t __aeabi_idivmod(int,int);
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}
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bool
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ICBinaryArith_Int32::Compiler::generateStubCode(MacroAssembler& masm)
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{
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// Guard that R0 is an integer and R1 is an integer.
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Label failure;
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masm.branchTestInt32(Assembler::NotEqual, R0, &failure);
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masm.branchTestInt32(Assembler::NotEqual, R1, &failure);
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// Add R0 and R1. Don't need to explicitly unbox, just use R2's payloadReg.
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Register scratchReg = R2.payloadReg();
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// DIV and MOD need an extra non-volatile ValueOperand to hold R0.
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AllocatableGeneralRegisterSet savedRegs(availableGeneralRegs(2));
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savedRegs.set() = GeneralRegisterSet::Intersect(GeneralRegisterSet::NonVolatile(), savedRegs.set());
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ValueOperand savedValue = savedRegs.takeAnyValue();
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Label maybeNegZero, revertRegister;
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switch(op_) {
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case JSOP_ADD:
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masm.ma_add(R0.payloadReg(), R1.payloadReg(), scratchReg, SetCC);
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// Just jump to failure on overflow. R0 and R1 are preserved, so we can
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// just jump to the next stub.
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masm.j(Assembler::Overflow, &failure);
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// Box the result and return. We know R0.typeReg() already contains the
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// integer tag, so we just need to move the result value into place.
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masm.mov(scratchReg, R0.payloadReg());
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break;
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case JSOP_SUB:
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masm.ma_sub(R0.payloadReg(), R1.payloadReg(), scratchReg, SetCC);
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masm.j(Assembler::Overflow, &failure);
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masm.mov(scratchReg, R0.payloadReg());
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break;
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case JSOP_MUL: {
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ScratchRegisterScope scratch(masm);
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Assembler::Condition cond = masm.ma_check_mul(R0.payloadReg(), R1.payloadReg(), scratchReg,
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scratch, Assembler::Overflow);
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masm.j(cond, &failure);
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masm.as_cmp(scratchReg, Imm8(0));
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masm.j(Assembler::Equal, &maybeNegZero);
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masm.mov(scratchReg, R0.payloadReg());
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break;
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}
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case JSOP_DIV:
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case JSOP_MOD: {
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// Check for INT_MIN / -1, it results in a double.
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{
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ScratchRegisterScope scratch(masm);
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masm.ma_cmp(R0.payloadReg(), Imm32(INT_MIN), scratch);
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masm.ma_cmp(R1.payloadReg(), Imm32(-1), scratch, Assembler::Equal);
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masm.j(Assembler::Equal, &failure);
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}
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// Check for both division by zero and 0 / X with X < 0 (results in -0).
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masm.as_cmp(R1.payloadReg(), Imm8(0));
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masm.as_cmp(R0.payloadReg(), Imm8(0), Assembler::LessThan);
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masm.j(Assembler::Equal, &failure);
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// The call will preserve registers r4-r11. Save R0 and the link
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// register.
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MOZ_ASSERT(R1 == ValueOperand(r5, r4));
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MOZ_ASSERT(R0 == ValueOperand(r3, r2));
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masm.moveValue(R0, savedValue);
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masm.setupAlignedABICall();
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masm.passABIArg(R0.payloadReg());
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masm.passABIArg(R1.payloadReg());
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masm.callWithABI(JS_FUNC_TO_DATA_PTR(void*, __aeabi_idivmod));
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// idivmod returns the quotient in r0, and the remainder in r1.
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if (op_ == JSOP_DIV) {
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// Result is a double if the remainder != 0.
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masm.branch32(Assembler::NotEqual, r1, Imm32(0), &revertRegister);
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masm.tagValue(JSVAL_TYPE_INT32, r0, R0);
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} else {
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// If X % Y == 0 and X < 0, the result is -0.
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Label done;
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masm.branch32(Assembler::NotEqual, r1, Imm32(0), &done);
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masm.branch32(Assembler::LessThan, savedValue.payloadReg(), Imm32(0), &revertRegister);
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masm.bind(&done);
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masm.tagValue(JSVAL_TYPE_INT32, r1, R0);
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}
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break;
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}
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case JSOP_BITOR:
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masm.ma_orr(R1.payloadReg(), R0.payloadReg(), R0.payloadReg());
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break;
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case JSOP_BITXOR:
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masm.ma_eor(R1.payloadReg(), R0.payloadReg(), R0.payloadReg());
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break;
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case JSOP_BITAND:
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masm.ma_and(R1.payloadReg(), R0.payloadReg(), R0.payloadReg());
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break;
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case JSOP_LSH:
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// ARM will happily try to shift by more than 0x1f.
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masm.as_and(R1.payloadReg(), R1.payloadReg(), Imm8(0x1F));
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masm.ma_lsl(R1.payloadReg(), R0.payloadReg(), R0.payloadReg());
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break;
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case JSOP_RSH:
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masm.as_and(R1.payloadReg(), R1.payloadReg(), Imm8(0x1F));
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masm.ma_asr(R1.payloadReg(), R0.payloadReg(), R0.payloadReg());
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break;
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case JSOP_URSH:
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masm.as_and(scratchReg, R1.payloadReg(), Imm8(0x1F));
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masm.ma_lsr(scratchReg, R0.payloadReg(), scratchReg);
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masm.as_cmp(scratchReg, Imm8(0));
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if (allowDouble_) {
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Label toUint;
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masm.j(Assembler::LessThan, &toUint);
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// Move result and box for return.
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masm.mov(scratchReg, R0.payloadReg());
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EmitReturnFromIC(masm);
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masm.bind(&toUint);
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ScratchDoubleScope scratchDouble(masm);
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masm.convertUInt32ToDouble(scratchReg, scratchDouble);
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masm.boxDouble(scratchDouble, R0);
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} else {
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masm.j(Assembler::LessThan, &failure);
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// Move result for return.
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masm.mov(scratchReg, R0.payloadReg());
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}
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break;
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default:
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MOZ_CRASH("Unhandled op for BinaryArith_Int32.");
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}
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EmitReturnFromIC(masm);
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switch (op_) {
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case JSOP_MUL:
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masm.bind(&maybeNegZero);
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// Result is -0 if exactly one of lhs or rhs is negative.
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masm.ma_cmn(R0.payloadReg(), R1.payloadReg());
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masm.j(Assembler::Signed, &failure);
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// Result is +0.
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masm.ma_mov(Imm32(0), R0.payloadReg());
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EmitReturnFromIC(masm);
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break;
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case JSOP_DIV:
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case JSOP_MOD:
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masm.bind(&revertRegister);
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masm.moveValue(savedValue, R0);
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break;
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default:
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break;
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}
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// Failure case - jump to next stub.
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masm.bind(&failure);
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EmitStubGuardFailure(masm);
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return true;
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}
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bool
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ICUnaryArith_Int32::Compiler::generateStubCode(MacroAssembler& masm)
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{
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Label failure;
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masm.branchTestInt32(Assembler::NotEqual, R0, &failure);
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switch (op) {
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case JSOP_BITNOT:
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masm.ma_mvn(R0.payloadReg(), R0.payloadReg());
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break;
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case JSOP_NEG:
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// Guard against 0 and MIN_INT, both result in a double.
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masm.branchTest32(Assembler::Zero, R0.payloadReg(), Imm32(0x7fffffff), &failure);
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// Compile -x as 0 - x.
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masm.as_rsb(R0.payloadReg(), R0.payloadReg(), Imm8(0));
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break;
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case JSOP_INC: {
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RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.payloadReg());
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masm.inc32(&rval);
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break;
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}
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case JSOP_DEC: {
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RegisterOrInt32Constant rval = RegisterOrInt32Constant(R0.payloadReg());
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masm.dec32(&rval);
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break;
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}
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default:
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MOZ_CRASH("Unexpected op");
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}
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EmitReturnFromIC(masm);
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masm.bind(&failure);
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EmitStubGuardFailure(masm);
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return true;
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}
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} // namespace jit
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} // namespace js
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